1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to those capable of rapid operation.
2. Description of the Background Art
As semiconductor integrated device technology has developed, the elements and interconnects formed on a semiconductor substrate have been increasingly microfabricated and increasing the storage capacity has been contemplated. In such semiconductor memory devices, in order to achieve rapid access time a transition (a rising) of a dummy word line providing the identical operation to a word line can be detected to time a read operation or the like. For example, Japanese Patent Laying-Open No. 60-76095 describes an example which applies this technique to a DRAM.
FIG. 2 is a simple block diagram of a semiconductor memory device provided with a detection technique using a conventional dummy word line. FIG. 3 shows an example of circuit configuration specifically showing a portion thereof FIG. 4 represents a waveform of operation. While an example is herein described using a mask ROM, which is relatively simple in configuration, the present invention is not limited thereto.
Referring to FIGS. 2-4, in the conventional mask ROM, addresses Ai, Ai+1 and the like input external to the chip are input to an address buffer 1. Address buffer 1 detects a transition of each address and outputs a pulsed signal ATD to a timing generator 10. Signal ATD is generated when any address changes. Timing generator 10 refers to signal ATD to generate various internal signals and operates in internal synchronization. Address buffer 1 also outputs internal address signals ADi, ADi/ and the like to an address decoder 2. When address decoder 2 receives the internal address signals, it drives a word line 6 and outputs a column select signal to a column selector 8. In response to the column select signal, column selector 8 selects a predetermined bit line 5 (a column). Thus in a memory cell array 3 a memory 4 specified by word line 6 and bit line 5 is read out.
Timing generator 10 receives signal ATD to generate various timing signals. For example, it generates an internal signal CKP to precharge, equalize and the like a bit line, and it also generates an internal signal OHZ (an output enable signal) to activate an output buffer 13. A sense amplifier 9 precharges and equalizes a bit line when internal signal CKP is held high, and sense amplifier 9 provides sensing and amplification when internal signal CKP is held low. More specifically, in response to a signal generated by timing generator 10, sense amplifier 9 precharges and equalizes a bit line selected by column selector 8 and senses and amplifies data of the bit line. Output buffer 13 outputs an output from sense amplifier 9 to outside the chip when internal signal OHZ is held low, and output buffer 13 places an output terminal in high impedance state when internal signal OHZ is held high.
A dummy word line drive circuit 11 responds to a start signal ATDX output from timing generator 10 to drive a dummy word line 7 at the same timing as address decoder 7 drives a word line, ant it inactivates dummy word line 7 in response to an internal signal RSDWL. A detector 12 detecting a low to high transition of a dummy word line outputs a detection signal PRE when it detects that dummy word line 7 attains a predetermined reference potential.
FIG. 5 shows an exemplary circuit configuration of detector 12 detecting a low to high transition of a dummy word line. Dummy word line detection circuit 12 compares a potential of dummy word line DWL to a predetermined reference potential VREF2 at an end of the dummy word line to generate a detection signal PRE. In this configuration, detection signal PRE is held low when dummy word line DWL is of low level (DWL&lt;VREF2), and detection signal PRE is rapidly inverted high when the potential of dummy word line DWL gradually increases and matches the reference potential (DWL=VREF2). It should be noted that reference potential VREF2 is determined depending on a resistance obtained by dividing resistances R3 and R4. For example, for R3=2 k.OMEGA. and R4=8 k.OMEGA., VREF2=(4/5)Vcc. When detection signal PRE goes high, it can be determined that the potential of word line WL has increased sufficiently. Thus, internal signal CKP is set low to terminate precharging and equalization and also allow a sense amplifier to read a value of a bit line. When the sense amplifier is reading it, the output terminal is held in high impedance (HiZ) state by internal signal OHZ. At a timing when the read completes, internal signal OHZ is set low and internal signal RSDWL is also set high. When internal signal RSDWL goes high, dummy word line drive circuit 11 allows dummy word line DWL to rapidly transition inactive low. When the potential of dummy word line DWL drops below the predetermined reference potential VREF2, dummy word line detection circuit 12 inverts detection signal PRE to low.
Thus, the detection of a low to high transition of dummy word line, the termination of precharging and equalization, the provision of a read operation by a sense amplifier, and the provision a series of operations to stop the sense amplifier after the read completes can reduce current consumption.
In the conventional mask ROM, 1-bit information is previously stored in one memory transistor 4 fabricated according to a mask pattern in manufacturing it. The information is read by sensing via sense amplifier 9 whether memory transistor 4 accessed is ON or OFF. Since the aforementioned microfabrication of devices reduces the memory transistor 4 drive current, the reading level will further be reduced. In order to maximize the memory transistor 4 drive current, word line 6 coupled with the gate of memory transistor 4 should have a sufficiently high level (a level close to the Vcc level). When word line 6 is a wiring layer containing, e.g., conductive polysilicon, however, the resistance value thereof is larger than that of a metal or aluminum wire and also varies in manufacturing word line 6. Thus it is difficult to determine whether the level of the end of word line 6 has risen to a predetermined level when word line 6 is accessed. Thus, rather than detect a low to high transition of the level at the end of word line 6, dummy word line 7 identical in structure to a word line is generally employed to detect a level at an end of dummy word line 7 via dummy word line detector 12.
Hereinafter, to readily understand the present invention, identical circuits and the like in the description and the drawings are denoted by same reference characters.
A rising waveform of such a conventional dummy word line DWL is the same as that of word line WL. Thus, for example, when a sufficient rise in level at an end of a word line, i.e., a rise to voltage VREF2 is adapted to be detected, as shown in FIG. 6, a variation .DELTA.V of reference voltage VREF2 due to a variation in manufacture, a variation in temperature or the like results in a variation .DELTA.T2 of detection signal PRE and reference VREF2 closer to the power supply potential disadvantageously increases .DELTA.T2 if .DELTA.V does not change. Since access time of a semiconductor memory device should be defined depending on the worst case (the worst value), it is difficult to rapidly operate the semiconductor memory device. Selecting a rapidly operating device also results in reduction in yield.